ASIC Engineer New Grad
ASIC Physical Design
- LocationBengaluru, Karnataka, India
- TypeFull-time
- ExperienceGraduating 2027
- SalaryNot disclosed
SystemVerilog, C++, Python, UVM, RTL To GDSII Flow, RTL, ASIC, Physical Design, Data Structures, Algorithms
Overview
Design and verify next-generation networking chips used in Cisco's core products. Focus on advanced process nodes and complex technical challenges in physical design. Work on timing closure, power integrity, and automation for high-speed switches and routers.
Summarised by InternDoor from Cisco’s posting, in our own words. The posting itself is the source of truth, so check it before you apply.
Responsibilities
- Implement RTL2GDS flow for high-speed networking chips
- Work with 5/3/2 nm technologies and advanced process nodes
- Collaborate on timing closure and power integrity for multimillion gate ASICs
Requirements
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Academic criteria
- Graduation year Eligibility: The requirement is for 2027 graduates only
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How to apply
- Check what they ask for. Read the requirements above: Cisco asks for Graduating 2027.
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Application details
- Posted
- , on LinkedIn
- First seen by InternDoor
- , within 42 minutes of being posted
- Last checked
- : the posting was still in LinkedIn’s search results. We have not checked its application page.
- Application deadline
- Cisco has not stated one
- Leaves InternDoor
- By , our 30-day limit for LinkedIn listings, or sooner if the application closes
- Application page
- careers.cisco.com
What we checked, and what the dates mean
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InternDoor has recorded 69 engineering postings from Cisco in India since Aug 2026.
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