Texas Instruments interview prep

6 practice questions on the topics candidates reported from Texas Instruments interviews, with answers. The questions are ours; each one links to the interview report that names its topic.

Practise them as a timed round 5 roles open at Texas Instruments India

C and C++ 4

C and C++Medium

What does this print on a little-endian machine such as an x86 or ARM laptop?
```
#include <stdio.h>

int main(void) {
    unsigned int x = 0x11223344;
    unsigned char *p = (unsigned char *)&x;
    printf("%x", p[0]);
    return 0;
}
```
1. 11
2. 44
3. 1122
4. 0
Show the answer

B. 44

Little-endian stores the least significant byte at the lowest address, so the first byte of x is 0x44. On a big-endian machine p[0] would be 0x11; checking that first byte is the usual endianness test.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.
C and C++Medium

On a typical system with 4-byte ints aligned to 4 bytes, what does this print?
```
#include <stdio.h>

struct S {
    char a;
    int b;
    char c;
};

int main(void) {
    printf("%zu", sizeof(struct S));
    return 0;
}
```
1. 6
2. 9
3. 12
4. 8
Show the answer

C. 12

b must start at a multiple of 4, so 3 padding bytes follow a. c takes 1 byte and 3 more pad the struct to a multiple of its 4-byte alignment, so arrays of S stay aligned: 1 + 3 + 4 + 1 + 3 = 12. Ordering members largest first would shrink it to 8.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.
C and C++Hard

An aligned allocator rounds an address up to the next multiple of a power-of-two alignment with (addr + align - 1) & ~(align - 1). What is 0x1003 rounded up to a 16-byte boundary?
1. 0x1000
2. 0x1004
3. 0x1013
4. 0x1010
Show the answer

D. 0x1010

0x1003 + 15 = 0x1012, and clearing the low 4 bits gives 0x1010. An address that is already aligned is left unchanged, since adding 15 never reaches the next boundary.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.
C and C++Medium

Embedded C code must read the 32-bit hardware register at address 0x40021000. Which expression reads it correctly?
1. *(volatile uint32_t *)0x40021000
2. (uint32_t)0x40021000
3. &0x40021000
4. *(uint8_t)0x40021000
Show the answer

A. *(volatile uint32_t *)0x40021000

Cast the number to a pointer to a 32-bit unsigned type, then dereference it. volatile makes the compiler perform the read every time instead of reusing an earlier value. The second option is just the number itself, not the register's contents.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.

Operating systems 2

Operating systemsMedium

Two CPU cores each cache the same memory location. One core writes to it. What is the cache coherence problem?
1. The two cores deadlock on the location
2. The cache becomes too small to hold the value
3. The write goes to the disk instead of RAM
4. The other core may keep reading its own stale cached copy unless that copy is invalidated or updated
Show the answer

D. The other core may keep reading its own stale cached copy unless that copy is invalidated or updated

Coherence protocols such as MESI invalidate other cores' copies when one core writes. Hardware such as a DMA engine can also change memory behind the cache, which is why drivers call cache invalidate or flush routines.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.
Operating systemsHard

A DMA controller writes incoming data into a RAM buffer that the CPU may still hold in its cache. What must the driver do before the CPU reads the buffer?
1. Nothing; the CPU always reads RAM directly
2. Flush the CPU cache to disk
3. Invalidate the cache lines covering the buffer, so the CPU re-reads the new data from RAM instead of a stale cached copy
4. Disable interrupts for the duration of the read
Show the answer

C. Invalidate the cache lines covering the buffer, so the CPU re-reads the new data from RAM instead of a stale cached copy

DMA bypasses the CPU cache on systems without hardware coherence. Before the CPU reads DMA-written memory the lines are invalidated; before a device reads CPU-written memory they are cleaned (flushed) to RAM.

This topic is named in a candidate’s interview report: Software engineer on-campus interview, 2021, on GeeksforGeeks.

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C and C++ 4

What does this print on a little-endian machine such as an x86 or ARM laptop?

On a typical system with 4-byte ints aligned to 4 bytes, what does this print?

An aligned allocator rounds an address up to the next multiple of a power-of-two alignment with (addr + align - 1) & ~(align - 1). What is 0x1003 rounded up to a 16-byte boundary?

Embedded C code must read the 32-bit hardware register at address 0x40021000. Which expression reads it correctly?

Operating systems 2

Two CPU cores each cache the same memory location. One core writes to it. What is the cache coherence problem?

A DMA controller writes incoming data into a RAM buffer that the CPU may still hold in its cache. What must the driver do before the CPU reads the buffer?

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