ASIC Design Engineer Intern
Logic Design
Posted Unpaid4 clicked applyOn-site
The gist
This internship involves designing and verifying complex logic for AI vision processors. Ideal for students with a master’s in electrical or computer engineering and experience in Verilog and System Verilog. The role includes RTL optimization and test development.
What you would actually do
- Design video compression and AI accelerator logic in Verilog/System Verilog
- Develop test benches and verification flows with UVM and C++
- Optimize RTL for timing, area, and power
- Participate in chip bring-up and testing
Skills mentioned
verilogsystem verilogperluvmc++
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.