SOC DFT Intern - Summer 2027
DFT Implementation
Posted
Open nowConfirmed on NXP Semiconductors’s own careers page · checked
The gist
This internship involves supporting DFT methodologies for SoC designs, working with engineers on scan insertion, ATPG, and test coverage analysis. Ideal for students with a background in digital logic and VLSI, seeking hands-on experience with industry tools.
What you would actually do
- Implement DFT techniques like scan insertion and memory BIST
- Use Python, Perl, TCL for automation and ATPG pattern generation
- Collaborate with RTL and verification teams on testability
Skills mentioned
How to apply
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This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.
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