Intern - HBM SoC RTL Design Engineer
SoC RTL Design
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
What stands out
- Pay is stated up front — $39 – $50 / hour. Most postings never say.
- Posted in the last 24 hours.
The gist
This internship involves designing RTL for HBM SoC logic die, working with SystemVerilog and EDA tools. It suits students with a background in electrical engineering or computer engineering seeking hands-on experience in SoC integration.
What you would actually do
- Design and implement RTL for HBM SoC logic die blocks
- Use SystemVerilog/Verilog with Cadence, Synopsys, Siemens tools
- Work with architects, verification, and firmware teams
Skills mentioned
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.