Design Verification Intern, BS - Summer 2027
Chip Verification
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
What stands out
- Pay is stated up front — $30 – $59 / hour. Most postings never say.
- Posted in the last 24 hours.
- The same role is open in 4 locations.
The gist
This role involves writing and debugging testbenches for SOC designs using UVM methodology. You'll simulate and analyze chip behavior with industry tools and collaborate with chip architects on verification and debugging. Ideal for students with a strong background in computer architecture and verification principles.
What you would actually do
- Write and debug testbenches using UVM methodology for SOC designs
- Simulate and analyze chip behavior with Synopsys, Cadence, and Mentor tools
- Collaborate with chip architects on verification and debugging
- Work on next-gen cloud, AI, and networking technologies
Skills mentioned
About this listing
- Found on
- First seen by InternDoor
- , within 3 hours of being posted
- Last seen listed
- Application page
- marvell.wd1.myworkdayjobs.com
InternDoor has recorded 100 engineering postings from Marvell Technology in the US since Aug 2026. LinkedIn listings stay on InternDoor for at most 30 days after we first see them, so this one comes down by , or sooner if we find its application has closed. When it comes down, this address points to Marvell Technology’s page instead of a dead end.
How to apply
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This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.