ASIC Design-for-Test (DFT) Engineer Intern
ASIC DFT Engineer
Posted $40 – $432 clicked applyOn-site
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
What stands out
- Pay is stated up front — $40 – $43. Most postings never say.
- Only 2 people had applied when this was listed.
- Posted in the last 24 hours.
The gist
This internship offers hands-on experience in ASIC DFT methodologies, working with industry-standard tools and teams. Ideal for students with a technical background in digital design and a passion for semiconductor development.
What you would actually do
- Support DFT architecture development for digital and mixed-signal ASICs
- Use Siemens Tessent and other EDA tools for ATPG and test pattern generation
- Collaborate with design and verification teams on testability requirements
- Based in Colorado Springs
Skills mentioned
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.