Physical Design Engineer I (Co-op) - United States
ASIC Design
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
What stands out
- Pay is stated up front — $44,000 – $185,000. Most postings never say.
- Posted in the last 24 hours.
The gist
This co-op role involves optimizing ASIC designs for high-capacity networks. You'll work on physical implementation, timing closure, and power efficiency. Ideal for students with a background in electrical engineering or computer science looking to gain hands-on experience in VLSI design.
What you would actually do
- Optimize power, performance, and area of ASIC designs
- Work with front-end teams on physical implementation and timing closure
- Use tools for floorplanning, routing, and static timing analysis
Skills mentioned
About this listing
- Found on
- First seen by InternDoor
- , within 2 hours of being posted
- Last seen listed
- Application page
- careers.cisco.com
InternDoor has recorded 63 engineering postings from Cisco in the US since Aug 2026. LinkedIn listings stay on InternDoor for at most 30 days after we first see them, so this one comes down by , or sooner if we find its application has closed. When it comes down, this address points to Cisco’s page instead of a dead end.
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.