Junior Layout Design Engineer (Trainee)
IC Layout Design
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
The gist
This internship involves designing and verifying IC layouts for analog and mixed-signal chips. You'll work with engineers on mask design, learn industry tools, and gain hands-on experience in layout creation and verification. Ideal for students interested in semiconductor design and layout engineering.
What you would actually do
- Create full chip floor plans and verify layouts using Cadence Virtuoso
- Work with layout designers and engineers on mask design for analog ICs
- Learn Linux and Calibre tools for LVS, DRC, and antenna checks
Skills mentioned
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.