Verification Engineer Intern
Verification Engineering
Posted
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
The gist
This internship involves developing test benches and tools for complex socs with custom dsp and computer vision blocks. Ideal for master's students with experience in verilog, system verilog, and scripting languages.
What you would actually do
- Write and debug rtl logic for test benches
- Create tools and scripts for simulation analysis
- Develop random test generators for coverage
- Work on complex socs with custom dsp blocks
Skills mentioned
How to apply
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