ASIC Engineer Intern, Annapurna Labs - 2027
ASIC Design
Likely openWe list a role only while we believe it is still open. Confirm on the posting before you apply.
What stands out
- Pay is stated up front — $126,100 – $185,000 / year. Most postings never say.
- Only 6 people had applied when this was listed.
- Posted in the last 24 hours.
- The same role is open in 3 locations.
The gist
This internship involves designing and implementing digital logic blocks for custom silicon, working on real chip development projects. You'll collaborate with teams to bring design specifications to silicon, with mentorship and ownership of your project. Ideal for students with experience in hardware description languages and digital design.
What you would actually do
- Design RTL for digital logic blocks using Verilog/SystemVerilog
- Support synthesis, timing analysis, and physical design flows
- Collaborate with teams to turn design specs into silicon
- Mentorship and project ownership from day one
Skills mentioned
How to apply
Internships in the US often collect hundreds of applicants within a day, so applying early matters more than applying perfectly. A half-finished application sent on the first morning beats a polished one sent on the third.
This summary was written by InternDoor from the public posting, and is not the employer's own wording. The linked posting is the source of truth — check it before you apply.